The present disclosure relates to semiconductor devices and methods of fabricating the same. More particularly, the present disclosure relates to semiconductor nanowire field effect transistors and methods of fabricating the same.
Non-planar semiconductor devices such as FinFETs, trigates and gate-all around semiconductor nanowire field effect transistors are receiving considerable attention for possible use in extending conventional complementary metal oxide semiconductor (CMOS) scaling. One potential problem area for deeply scaled devices is band to band tunneling (i.e., gate induced drain tunneling or “GIDL” for short) which may limit how low an off current is obtainable for a given device. Low power technologies are particularly impacted by this, as the net off current from the sum of all devices on a chip contributes strongly to overall power consumption.